Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design mandatory for efficient systems. In designing low-energy dissipation circuits, reversible logic more than irreversible circuits but at cost higher complexity. This paper introduces an signed/unsigned 4 × Vedic multiplier with minimum quantum cost. The considered fast as it generates all partial product their sum one step. proposes two optimized garbage output. First, unsigned designed based on Urdhava Tiryakbhyam (UT) Sutra. consists bitwise multiplication adder compressors. Compared literature, proposed has a 111 reduction 94% compared to previous design. It output 30 optimization best-compared Second, expanded allow signed numbers well numbers. Two are presented aim obtaining performance parameters. DesignI separate binary two’s complement (B2C) MUX while DesignII combines circuit. shows lowest cost, 231, regarding state-of-the-art. 199, reducing 86.14% DesignI. functionality simulated verified using XILINX ISE 14.2.